(Not Applicable)
The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package including a flex circuit which allows multiple chip packages to be quickly, easily and inexpensively assembled into a chip stack having a minimal profile.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the xe2x80x9cfootprintxe2x80x9d typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant""s U.S. Pat. Nos. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages including flex circuits. The inclusion of the flex circuits in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significantly greater ease in achieving and maintaining the alignment between the chip packages within the stack. Additionally, the use of the flex circuits allows for the assembly of the chip packages into a chip stack which has a minimal profile.
In accordance with the present invention, there is provided a stackable integrated circuit chip package. The chip package comprises a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. The substrate is preferably fabricated from a polyamide which has a thickness of several mils or less, and may have a thickness down to about 1 mil. The substrate preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. Disposed on the top surface of the substrate is a first conductive pad array, while disposed on the bottom surface is a second conductive pad array. The first and second conductive pad arrays extend between the longitudinal peripheral edge segments in spaced relation to the lateral peripheral edge segments. Also disposed on the bottom surface of the substrate on opposite sides of the second conductive pad array are third and fourth conductive pad arrays which extend between the longitudinal peripheral edge segments along respective ones of the lateral peripheral edge segments. The third and fourth conductive pad arrays are each electrically connected to the second conductive pad array.
In the chip package of the present invention, the first conductive pad array preferably comprises a first set of pads, with the second conductive pad array preferably comprising a second set of pads which are arranged in an identical pattern to the first set of pads such that the pads of the first set are aligned (i.e., in registry with) respective ones of the pads of the second set. Similarly, the third conductive pad array comprises a third set of pads, with the fourth conductive pad array comprising a fourth set of pads. The third and fourth sets of pads are preferably arranged on the bottom surface of the substrate in patterns which are mirror images to each other. The pads of the third and fourth sets are electrically connected to respective ones of the pads of the second set through the use of conductive tracings.
The pads of the first through fourth sets and conductive tracings are preferably fabricated from very thin copper having a thickness in the range of from about 5 microns to about 25 microns through the use of conventional etching techniques. Advantageously, the use of the thin copper for the pads and conductive tracings allows for etching line widths and spacings down to a pitch of about 4 mils which substantially increases the routing density. The pads and tracings collectively define a conductive pattern of the flex circuit. Extending through the substrate between respective pairs of the pads of the first and second sets are a plurality of cross-slits, the use of which will be described in more detail below.
In addition to the flex circuit, the chip package of the present invention comprises an integrated circuit chip which is electrically connected to the first and second conductive pad arrays, and hence to the third and fourth conductive pad arrays by virtue of their electrical connection to the second conductive pad array via the conductive tracings. The integrated circuit chip preferably comprises a flip chip device or a fine pitch BGA (ball grid array) device having a body which is of a generally rectangular configuration defining opposed, generally planar top and bottom surfaces, a pair of longitudinal sides, and a pair of lateral sides. Protruding from the bottom surface of the body are a plurality of generally semi-spherically shaped conductive contacts which are preferably arranged in an identical pattern to the first and second sets of pads. In the present chip package, the electrical connection of the integrated circuit chip to the first and second conductive pad arrays is facilitated by the insertion of the conductive contacts into the cross-slits of respective ones of the pads of the first set, and advancement therethrough to protrude from respective ones of the pads of the second set and hence the bottom surface of the substrate.
In the chip package of the present invention, the substrate is wrapped about at least a portion of the integrated circuit chip such that the third and fourth conductive pad arrays collectively define a fifth conductive pad array which is electrically connectable to another stackable integrated circuit chip package. The fifth conductive pad array comprises the third and fourth sets of pads which, when the substrate is wrapped about the integrated circuit chip, are arranged in an identical pattern to the first and second sets of pads. The substrate is wrapped about the longitudinal sides of the body such that the fifth conductive pad array extends over the top surface of the body and the third and fourth sets of pads making up the fifth conductive pad array are in substantial alignment or registry with respective pairs of the first and second sets of pads.
The substrate is preferably sized relative to the integrated circuit chip such that the lateral peripheral edge segments of the substrate extend along the top surface of the body in generally parallel relation to each other and are separated by a narrow gap, with the lateral sides of the body being substantially flush with respective ones of the longitudinal peripheral edge segments of the substrate. As such, the integrated circuit chip is positioned upon the central portion of the substrate (which includes the first and second conductive pad arrays thereon), with the opposed end portions of the substrate (which include the third and fourth conductive pad arrays thereon) being wrapped about the integrated circuit chip so as to cover the top surface of the body thereof. These end portions of the substrate are preferably attached to the top surface of the body through the use of an adhesive. Additionally, the chip package may be provided with a pair of heat sinks which are attached to respective ones of the lateral sides of the body of the integrated circuit chip.
In addition to the end portions of the substrate being adhesively secured to the top surface of the body of the integrated circuit chip, the conductive contacts of the integrated circuit chip are preferably soldered to respective ones of the pads of the second set. In this respect, each of the conductive contacts may be pre-coated with solder paste or flux prior to the placement of the integrated circuit chip upon the first conductive pad array, with the application of heat to the chip package subsequent to the flex circuit being wrapped about the integrated circuit chip effectuating the soldering of the conductive contacts to the second set of pads, and hence the conductive pattern of the flex circuit.
Advantageously, those portions of the conductive contacts protruding from the pads of the second set and hence the bottom surface of the substrate may be electrically connected to respective ones of the conductive pads of a printed circuit board, or to respective ones of the third and fourth sets of pads of the fifth conductive pad array of another identically configured stackable integrated circuit chip package. In this respect, multiple chip packages of the present invention may be stacked upon one another, with solder paste or flux being pre-applied to the third and fourth sets of pads of the fifth conductive pad array prior to the stacking of another chip package thereupon such that the subsequent application of heat to the stack facilitates the desired electrical connection of the chip packages to each other. The engagement between the exposed portions of the conductive contacts and the third and fourth sets of pads of the fifth conductive pad array performs a self-aligning function during the soldering process, thus simply requiring that the longitudinal and lateral edges of the chip packages in the stack be aligned with each other prior to the application of heat thereto.
Those of ordinary skill in the art will recognize that the flex circuit need not necessarily be provided with the first conductive pad array in that the conductive contacts of the integrated circuit chip may be advanced through the cross-slits within the substrate and electrically mounted via soldering to only the pads of the second set forming the second conductive pad array. Additionally, the flex circuit may be adapted to be usable in conjunction with a bare die device by eliminating the cross-slits and electrically connecting the pads of the first set forming the first conductive pad array to respective ones of the pads of the second set forming the second pad array through the use of vias.